What is it and why is this characteristic needed in computer technology? Where did she find her application? How to achieve the best value of this characteristic?
About RAM
This is the name of a special device in which data is located and processes running while the computer is running are executed. Due to the speed of its action, it acts as an intermediary between the information located on the hard disk and the processor. The most understandable characteristic for most people is the amount of RAM. In this case, the rule works that the more it is, the better for us. In fact, now 2 GB is enough to use the Internet, watch movies and work with most useful programs. But a number of other parameters are also used to evaluate performance, such as frequency. It indicates how much data can be sent over the bus in one unit of time. The higher the frequency, the higher the information transfer rate. But it must be taken into account that it is also supported by the processor and motherboard. Or let's take another parameter, not so well known - latency. This is the name of the time delays of the signals that come from the random access memory. The lower the computer will work with, the better the result in terms of efficiency will eventually turn out.
Latency features
The previous paragraph missed one significant point. Along with the frequency of the RAM, the latency of the RAM also increases. Which one is better then OP? How to choose more or less universal indicators? It is considered optimal to use several memory models. So, if there are two of them, and they work in two-channel mode, then it will be increased. To do this, the boards used must be installed in certain slots (which, as a rule, are highlighted in one color). There is such a feature here: it is not necessary that they have the same amount of memory. But with regard to frequency, it is desirable to obtain a complete match here. Otherwise, they will work with the smallest value of the two.
What is memory latency
A little more theory. This is the name of summation, which is carried out using a special coefficient of uncontrolled reverse currents of transistors, which are included in each chip of the used memory line, as well as their switching time. This may sound complicated, but it's a misleading assumption. So, the latency depends on the frequency with which the chips work. Interestingly, it is not proportional. In other words: the lower the latency, the better for the user. Let's look at an example. We want our hypothetical to be two gigabytes in size. We can put one ruler, which will give us 2 GB. But this is not the best way. In this case, it would be best to install four lines, each 512 MB. In this case, the influence of the motherboard, as well as the types of RAM used, should also be taken into account. A module made on the basis of one technology cannot be placed in a place that is intended for another technology. This is implemented in order to exclude damage during the operation of a mechanism not intended for these conditions.
Designation
If you've ever looked at devices, you may have seen something similar to the following: "RAM latency: CL9". What does it mean? This indicator indicates a specific delay that occurs between the start of sending the address of the column to memory and, accordingly, the actual transfer of data. The number that is indicated indicates the amount needed to start this process. The smaller it is, the better for us. Therefore, when choosing RAM, this value must always be taken into account.
Device types
For separation by capabilities, a double data rate (DDR) is used, which can be translated as double data transfer rate. The very first samples of this technology had 184 contacts. Their standard supply voltage was 2.5 V. Samples 2 bits of data per cycle. But in our time they are considered obsolete and are now practically nowhere and under no circumstances are used. DDR2 is considered more modern and most common. It allows you to select 4 bits at once in one cycle. The module is made in the form that has 240 contacts (120 on each side). The standard supply voltage for it is 1.8 V. DDR3 is considered relatively new. It can sample 8 bits of data in one cycle. It is also made on a printed circuit board, which has 230 pins. But the standard supply voltage in this case is only 1.5 V. There is also DDR4, but this is a new technology that is still very difficult to meet.
Bandwidth
We will already complete the article about the latency of RAM. What was presented earlier is already enough to understand the bulk of the information about the OP. And as a finishing touch - throughput. So, ideally, the value of this characteristic on the part of the RAM should correspond to the size of the parameter on the processor. Consider this question, assuming that we have the previously mentioned two-channel mode. We have a processor with a throughput of 10600 Mb/s. Then we can install an operational module which will be 5300 Mb / s. Together they will provide the same amount of throughput. But do not forget that the modules must be of the same frequency. And it would be optimal if they also had the same volume, they were made by one manufacturer, and they were produced within the same batch. Then the latency of the RAM will tend to the minimum possible value. If we talk about that, they sell Kit specifically for these cases. This is the name of special sets that are already optimized for such work. It should be noted that you can also use memory, the bandwidth of which is higher than that of the processor. But this will not significantly affect latency, even if the difference is a multiple.
Conclusion
As you can see, RAM latency is a very important characteristic. Particularly pleasant is that it can be influenced not only from the hardware side, but also by choosing the configuration for your computer. But at the same time, it is still necessary to stay within reason and not work in more than a four-channel mode. No, of course, if you want, you can build a computer with 512 MB that can boast a processing speed of 8 GB. But the effectiveness of such a move would be rather doubtful. It is better to stop in this case at 4 boards, each of which will have 2 GB.
#Timings #CLIntroduction
DDR and DDR2 memory modules are classified by the maximum frequency they can run at. But, in addition to frequency, there are other parameters that determine memory performance - these are timings. Timings are numbers like 2-3-2-6-T1, 3-4-4-8 or 2-2-2-5, the lower the numbers the better. Let's see what each digit of these numbers means.
DDR and DDR2 memory modules are labeled DDRxxx/PCyyyy.
The first number, xxx, indicates the maximum clock speed at which the memory chips can operate. For example, the maximum frequency at which DDR400 modules can operate is 400 MHz, while DDR2-667 modules can operate at frequencies up to 667 MHz. It should be clarified that this is not the real clock frequency of the memory cells - their operating frequency in the case of DDR is half, and DDR2 is a quarter of the frequency indicated in the marking of the modules. That is, DDR400 memory modules operate at a frequency of 200 MHz, and DDR2-667 modules at a frequency of 166 MHz, but with a memory controller, both DDR and DDR-II communicate at half the frequency indicated in the marking (i.e. 200 and 333 MHz, respectively), therefore, in the future, it is this frequency that will be understood as the real working frequency.
The second number, yyyy, indicates the maximum data transfer rate in MB/s.
The maximum data transfer rate for DDR400 modules is 3200 MB / s, therefore, they are labeled PC3200. DDR2-667 modules transfer data at 5336MB/s and are labeled PC2-5400. As you can see, after "DDR" or "PC" we put the number "2" to indicate that we are talking about DDR2 memory, not DDR.
The first classification - DDRxxx - is the standard for the classification of memory chips, the second - PCyyyy - for memory modules. Figure 1 shows Corsair's PC2-4200 memory module, which is based on DDR2-533 chips.
DDR2-533/PC2-4200 memory module
The maximum operating frequency of a memory module can be calculated using the following formula:
maximum theoretical data rate = clock frequency x number of bits / 8
Since DIMMs transmit 64 bits at a time, the “number of bits” will be 64. Since 64 / 8 is 8, this formula can be simplified:
maximum theoretical data rate = clock frequency x 8
If a memory module is installed in a computer whose memory bus runs at a slower clock speed, then the maximum data transfer rate for that memory module will be lower than its maximum theoretical data transfer rate. In practice, misunderstanding of this fact is quite common.
For example, you bought 2 DDR500/PC4000 memory modules. Even though they are labeled DDR500, they will not automatically run at 500 MHz in your system. This is the maximum clock speed they support, but it doesn't always match the clock speed they will run at. If you install them in a regular personal computer that supports DDR modules, then these memory modules will operate at a frequency of 400 MHz (DDR400), the maximum frequency of the DDR standard. In this case, the maximum data transfer rate will be 3200 MB/s (or 6400 MB/s if the memory modules operate in dual-channel mode). Thus, the modules will not automatically operate at 500 MHz, and will not achieve a data rate of 4000 MB/s.
Why, in this case, such modules are bought? For overclocking. Since the manufacturer guarantees that these modules can operate at frequencies up to 500 MHz, you know that you can increase the memory bus frequency to 250 MHz, and thus increase the speed of the computer. But this can be done provided that the computer motherboard supports such overclocking. Therefore, if you do not want to "overclock" your computer, then it is useless to buy memory modules marked by a clock frequency higher than the usual motherboard memory bus frequency.
For the average user, this information about DDR/DDR2 memory modules is sufficient. An advanced user needs to know about one more characteristic: the speed of memory operation, or, as they also call the set of temporary parameters of memory operation - timings, delays or latency. Let's consider these parameters of memory modules in more detail.
Timings
It is precisely because of the difference in timings that 2 memory modules having the same theoretical maximum data transfer rate can have different bandwidth. Why is this possible if both modules operate at the same frequency?
To perform each operation, the memory chip needs quite a certain time - the timings just determine this time, expressed in the number of cycles of the memory bus clock frequency. Let's take an example. Consider the most famous parameter, which is called CAS Latency (or CL, or "access time"), which indicates how many clock cycles the memory module issues the data requested by the central processor. A memory module with CL 4 will be 4 clock cycles late in response, while a memory module with CL 3 will be 3 clock cycles late. While both modules can run at the same clock speed, the second module will run faster because it will output data faster than the first. This problem is known as "time out".
Memory timings are indicated by a series of numbers, such as 2-3-2-6-T1, 3-4-4-8 or 2-2-2-5. Each of these numbers indicates how many clock cycles the memory takes to perform a particular operation. The smaller these numbers, the faster the memory.
DDR2 memory module with 5-5-5-15 timings
Timing numbers indicate the parameters of the following operations: CL-tRCD-tRP-tRAS-CMD. To make it clearer, imagine that memory is organized as a two-dimensional matrix, where data is stored at the intersection of rows and columns.
CL: CAS Latency - the time elapsed from the moment the command was sent to memory until the start of the response to this request. That is, this is the time that elapses between the processor requesting some data from memory and the moment the memory issues this data.
tRCD: delay from RAS to CAS - the time that must pass from the moment the matrix row (RAS) is accessed until the matrix column (CAS) is accessed, in which the required data is stored.
tRP: RAS Precharge - the time interval from the moment of closing access to one row of the matrix and the beginning of access to another row of data.
tRAS– the pause that the memory needs to return to the state of waiting for the next request.
cmd: Command Rate - the time from the moment the memory chip is activated to the moment when it will be possible to access the memory with the first command. Sometimes this option is not specified. This is usually T1 (1 clock cycle) or T2 (2 clock cycles).
Usually the user has 2 options. When configuring your computer, use standard memory timings. In most cases, to do this, when setting up the motherboard in the memory configuration item, you need to select the "auto" option. You can also manually configure your computer with lower timings, which can improve system performance. It should be noted that not all motherboards allow you to change the memory timings. Also, some motherboards may not support very low timings, which may cause them to configure your memory module to run at higher timings.
Configuring memory timings in the motherboard settings
When overclocking memory, it may happen that in order for the system to work stably, you may need to increase the memory timings in the settings. This is where some very interesting situations can happen. Even though the memory frequency will be raised, due to the increase in memory latency, its bandwidth may decrease.
This is another advantage of high-speed overclocking-oriented memory modules. In addition to guaranteeing the operation of the memory module at the marked clock frequency, the manufacturer also guarantees that you will be able to keep the module's passport timings.
Going back to the DDR500/PC4000 memory module example - even though you can reach 500 MHz (250 MHz x2) with DDR400/PC3200 modules, they may need to increase their timings, while DDR500/PC3200 modules The PC4000 manufacturer guarantees that you will be able to reach 500 MHz while maintaining the timings indicated in the marking.
CAS Latency (CL)
As mentioned above, CAS Latency (CL) is a very important memory parameter. It indicates how many clock cycles the memory needs to provide the requested data. A memory with CL = 3 will delay responding by 3 clock cycles, while a memory with CL = 5 will only do the same after 5 clock cycles. Thus, of two memory modules running at the same clock speed, the one with the lower CL will be faster.
Please note that here the clock frequency refers to the actual clock frequency at which the memory module operates - that is, half of the indicated frequency. Since DDR and DDR2 memory can output data 2 times in one clock cycle, double the real clock frequency is indicated for them.
Figure 4 shows an example of how CL works. It shows 2 examples: for a memory module with CL = 3 and a memory module with CL = 5. The "read" command is indicated in blue.
CAS Latency (CL)
Memory with CL = 3 provides a 40% latency advantage over memory with CL = 5, assuming they are both running at the same clock speed.
You can even calculate the delay time after which the memory will start outputting data. The period of each clock cycle can be easily calculated using the following formula:
Thus, the period of one clock cycle of DDR2-533 memory operating at 533 MHz (bus frequency - 266.66 MHz) is 3.75 ns (ns = nanosecond; 1 ns = 0.000000001 s). Keep in mind that the calculation must use the actual clock frequency, which is half the nominal frequency. Thus, DDR2-533 memory will delay data output by 18.75 ns if CL = 5, and by 11.25 ns if CL = 3.
SDRAM, DDR, and DDR2 memory support burst data output, where the delay before the next piece of data is issued is only one clock cycle, if this data is located at the address following the current address. Therefore, while the first data is issued with a delay of CL clock cycles, the next data will be issued immediately after the first, not delayed by another CL cycles.
Delay from RAS to CAS (RAS to CAS Delay )
Each memory chip is internally organized as a two-dimensional matrix. At each intersection of rows and columns there is a small capacitor that is responsible for storing "0" or "1" - units of information, or data. The procedure for accessing data stored in memory is as follows: first, the row with the required data is activated, then the column. This activation occurs on two control signals - RAS (Row Address Strobe) and CAS (Column Address Strobe). The shorter the time interval between these two signals, the better, since the data will be read faster. This time is called the delay from RAS to CAS (RAS to CAS Delay). Figure 5 illustrates this, in this case for memory with tRCD = 3.
RAS to CAS Delay (tRCD)
As you can see, the latency from RAS to CAS is also the number of clock cycles from the arrival of the “Active” command to the “read” or “write” command.
As in the case of CAS Latency, RAS to CAS Delay deals with the actual clock frequency (which is half the marking frequency), and the lower this parameter, the faster the memory runs, since in this case the reading or writing of data begins faster.
RAS Precharge (tRP)
After receiving data from memory, a Precharge command must be sent to memory to close the memory line from which data was read and allow another line to be activated. RAS Precharge time (tRP) - the time interval between the Precharge command and the moment when the memory can accept the next activation command - Active. As we learned in the previous section, the "active" command starts a read or write cycle.
RAS Precharge (tRP)
Figure 6 shows an example for memory with tRCD = 3.
As with other parameters, RAS Precharge deals with the actual clock frequency (which is half the marking frequency), and the smaller this parameter, the faster the memory runs, since in this case the “active” command arrives faster.
Summing up the above, we get that the time that passes from the moment the Precharge command is issued (close the line and ...) until the processor actually receives data is tRP + tRCD + CL.
Other Options
Consider 2 other parameters - Active to Precharge Delay (tRAS) and Command Rate (CMD). As with the other parameters, these 2 parameters deal with the actual clock speed (which is half the marking frequency), and the lower these parameters, the faster the memory.
Active to Precharge Delay (tRAS): if an “Active” command is received in the memory, then the next “Precharge” command will not be accepted by the memory until a time equal to tRAS has passed. Thus, this parameter determines the time limit after which the memory can start reading (or writing) data from another row.
Command Rate (CMD) - the length of time from the moment the memory chip is activated (a signal arrives at the CS output - Chip Select [chip select]) until the chip can accept any command. This parameter is denoted by the letter “T” and can be set to 1T or 2T - 1 clock cycle or 2 clock cycles, respectively.
Introduction
This article is a continuation of the popular material "Influence of the amount of memory on computer performance", published on our website in April this year. In that material, we experimentally established that the amount of memory does not greatly affect the performance of a computer, and in principle, 512 MB is quite enough for ordinary applications. After the publication, our editors received many letters in which readers asked for advice on what kind of memory should be taken and whether it makes sense to buy more expensive memory, but with a smaller volume, and also asked to compare different types of memory.
And indeed, if in games the difference between the speeds of the same computer with 512 and 1024 MB of memory on board is scanty, maybe it is worth putting 512 MB of expensive memory than 1024 MB of cheap memory? In fact, the performance of the same memory module is affected by delays, the so-called timings. Usually the manufacturer indicates them with a hyphen: 4-2-2-8, 8-10-10-12 and so on. Overclocking memory for enthusiasts usually has low timings, but is quite expensive. Ordinary memory, which just works stably and does not promise speed records, has higher timings. This time we will find out what kind of timings are, delays between what and what and how they affect computer performance!
Memory delays
With the industry shifting to the DDR-II standard, many users reported that DDR-II memory did not perform as fast as they would like. Sometimes even slower than the previous generation memory, DDR-I. This was due precisely to the large delays of the first DDR-II modules. What are these delays? They are usually marked 4-4-4-12, four hyphenated numbers. They signify the following:
CAS Latency - RAS to CAS Delay - Row Precharge - Activate to Precharge
Let's try to clarify these notations. The memory bank consists of two-dimensional arrays. A two-dimensional array is the simplest matrix, each cell of which has its own address, row number and column number. To read the contents of a cell, the memory controller must first specify the row number and column number from which the data is read. To perform these operations, the controller must supply special signals to the memory.
RAS(Row Address Strobe) - a signal that determines the address of the row.
CAS(Column Address Strobe) - a signal that determines the address of the column.
CAS Latency(CAS) is the number of cycles from the moment the data is requested until it is read from the memory module. One of the most important characteristics of a memory module.
RAS to CAS Delay(TRCD) - delay between RAS and CAS signals. As we have already said, rows and columns are accessed separately from each other. This parameter determines the delay of one signal from another.
Row Precharge Delay(TRP) - the delay required to recharge the capacities of the memory cells. Produces or closes the entire line.
Activate to Precharge(TRAS) - strobe active time. The minimum number of cycles between an activation command (RAS) and a precharge command (Precharge) or close of the same bank.
The lower these timings, the correspondingly better: the memory will run faster with low latency. But how much better and how much faster, you need to check.
Memory for speed
The BIOS of modern motherboards allows you to manually change the timings. The main thing is that the memory modules support these values. By default, the timing values are "hardcoded" into the SPD chips of the modules, and the motherboard automatically sets the values recommended by the manufacturer. But nothing prevents enthusiasts from reducing delays manually by overclocking the memory a little. Often this leads to unstable operation. Therefore, in order to compare the impact of timings on speed, we will take a very fast memory and we will safely slow it down by changing certain delays.
This is a modern platform designed for use in computers with high performance. It is based on the Intel i925X chipset, which supports only DDR-2 memory and uses PAT optimization technologies. The ventilation is very well calculated in this computer, so we did not have to be afraid of overheating.
test system
- Intel Pentium 4 2.8 GHz (800 MHz FSB, 1024 Kb L2, LGA 775)
- 80 Gb Maxtor DiamondMax 9 (7200 RPM, 8 Mb) S-ATA
- SAPPHIRE RX600 PRO 128Mb PCI Express
- Windows XP Professional (Eng.) SP2
- CATALYST 5.3
You need to test memory in different applications to see the difference in speed, or vice versa to show that it does not exist. Here we need the following tests:
RightMark Memory Analyzer
SiSoft Sandra 2005
PCMark 2004 patch 120
Realworld test
Synthetics
Emulation of real tasks
Well, lots of plans! Let's start with synthetics.
Write to Read Turnaround Time(tW2R)
Time between write and read, with read interrupted by write.
The peculiarity of the interval is that to interrupt reading, you need to issue the Burst Terminate command, and the minimum interval from this command to the write procedure is called RU (CL) (where CL - CAS Latency and RU - Round Up to the nearest integer, BST - Burst Terminate ). Procedure diagram below:
Write to Read Turnaround Time for Same Bank(tW2RSame Bank)
Similar to the previous procedure, differing from it only in that the action takes place in the same bank. The peculiarity of the delay is that the writing procedure, of course, cannot be longer than the interval before the bank is recharged (tWR), that is, it ends during the recharge.
Read to Read Turnaround Time(tR2R)
The delay when a read operation is interrupted by a read from another bank.
Row Cycle Time, Activate to Activate/Refresh Time, Active to Active/Auto Refresh Time(tRC)
Time for automatic recharging. Found in datasheets.
Auto Refresh Row Cycle Time, Refresh to Activate/Refresh Command Period, Refresh Cycle Time, Refresh to Active/Refresh Command Period(tRFC)
The minimum interval between a command to recharge (Refresh) and either the next command to recharge or the command to activate.
Memory Refresh Rate
Memory refresh rate.
Practice
So, we have considered the main timings that we can most often meet in programs or datasheets. Now, for the full picture, I will tell you how timings are useful in overclocking.
It is known that by increasing the timings, we can increase the memory frequency, and vice versa, by lowering the timings, the overclocking limit worsens. Regular RAM is overclocked like this: first, the maximum processor frequency is found, then the memory frequency, and then the minimum timings.
Which is better - high frequency or minimum timings? Our answer to this question is:
"There is an opinion that for Intel" timings are more important, while for AMD - frequency. In particular, ALT-F13 (guru from www.ModLabs.net) states: "The best option for Intel is the most aggressive timings. So much so that async with 2-5-2-2 drives sync with 2.5-7-3-3 any FSB (i.e. - 280 3-7-3-3 at 1:1 is worse than 230 2-5-2-2 at 5:4)".
At the same time, one should not forget that for AMD, most often, the memory frequency is important not just any, but the one achieved in synchronous mode.
Although the result will be different on each system. In general, experiment.
For video memory, there are aspects of overclocking. So, to achieve higher frequencies, it is not forbidden to even raise the timings, since the performance drop will be minimal. More details about such overclocking of video memory are described in this article, and a discussion of this method is in the conference thread.
And the last thing: in the forums there are often designations like 2-3-3-7. So, these are indicators of the main characteristics of memory:
(Picture from the site www.thg.ru). Here the timings are listed in order of importance.
I decided to investigate the influence of timings on my system.
So here she is:
The system was left "as is". The video card also did not overclock. The tests were carried out in two test packages and in one game:
- 3DMark 2001 patch 360, as it evaluates the overclocking of every element of the system, and not just the video card
SiSoft Sandra 2001 SP1 - Memory Bandwidth Benchmark, evaluates memory bandwidth
FarCry v.1.3 - Research Demo, used as a real game application.
"Overclocker" for its time memory NCP and this time did not miss and allowed to run at a frequency of 143 MHz with timings 2-2-2-7! But the memory does not change the last parameter (Tras) for any reason, only with a decrease in frequency. However, this is not the most important parameter.
As you can see, lowering the timings gives a performance increase of about 10%. And if on my system this is not so noticeable, then on a more powerful one the difference is already becoming obvious. And if you change the timings on the video card, where overclocking often rests not on memory, but just on delays, then the work will be more than justified. And what exactly is changing, now you already know.
Comments on the article, as always, I accept
Today we will talk about the most accurate definition of timings and sub-timings. Most articles on the net have errors and inaccuracies, and very worthy materials do not always cover all timings. We will try to fill this gap and give as complete a description of one or another time delay as possible.
The memory structure resembles a table, where a row is selected first, and then a column. This table is divided into banks, for memory with a density less than 64Mbit (SDRAM) there are 2 pieces, above - 4 (standard). The specification for DDR2 SDRAM memory with 1Gbit density chips already provides for 8 banks. It takes more time to open a line in the used bank than in another (because the used line must be closed first). Obviously, it is better to open a new line in a new bank (the principle of line alternation is based on this).
Usually on the memory (or in the specification for it) there is an inscription like 3-4-4-8 or 5-5-5-15. This is an abbreviated record (the so-called timing scheme) of the main memory timings. What are timings? Obviously, no device can run at infinite speed. This means that any operation takes some time to complete. Timings is a delay that sets the time required to execute a command, that is, the time from sending a command to its execution. And each number indicates exactly how long it takes.
Now let's take each one in turn. The timing scheme includes CL-Trcd-Trp-Tras delays, respectively. To work with memory, you must first select the chip with which we will work. This is done with the CS# (Chip Select) command. Then the bank and line are selected. Before you can work with any line, you must activate it. This is done by the RAS# row selection command (it is activated when a row is selected). Then (during a linear read operation), you need to select a column with the CAS# command (the same command initiates a read). Then read the data and close the line by pre-charging the bank.
The timings are arranged in order in the simplest query (for ease of understanding). Timings come first, then sub-timings.
Trcd, RAS to CAS delay- the time required to activate the row of the bank, or the minimum time between the signal to select the row (RAS#) and the signal to select the column (CAS#).
CL, Cas Latency- the minimum time between the issuance of a read command (CAS) and the start of data transfer (read latency).
Tras, Active to Precharge- the minimum time of row activity, that is, the minimum time between the activation of the row (its opening) and the command for pre-charge (the beginning of the closing of the row). The row cannot be closed before this time.
Trp, Row Precharge- the time required to pre-charge the bank (precharge). In other words, the minimum row closing time after which a new bank row can be activated.
CR, Command Rate 1/2T- The time required for the controller to decode commands and addresses. Otherwise, the minimum time between two commands. With a value of 1T, the command is recognized for 1 cycle, with 2T - 2 cycles, 3T - 3 cycles (so far only on the RD600).
These are all basic timings. The rest of the timings have a lesser effect on performance, and therefore they are called sub-timings.
Trc, Row Cycle Time, Activate to Activate/Refresh Time, Active to Active/Auto Refresh Time - minimum time between activation of rows of the same bank. It is a combination of Tras+Trp timings - the minimum time the line is active and the time it closes (after which you can open a new one).
Trfc, Row Refresh Cycle Time, Auto Refresh Row Cycle Time, Refresh to Activate/Refresh Command Period - minimum time between a command to update a row and an activation command or another update command.
Trd, ACTIVE bank A to ACTIVE bank B command, RAS to RAS Delay, Row Active to Row Active - minimum time between activation of rows of different banks. Architecturally, you can open a line in another bank immediately after opening a line in the first bank. The limitation is purely electrical - it takes a lot of energy to activate, and therefore, with frequent activation of the strings, the electrical load on the circuit is very high. To reduce it, this delay was introduced. Used to implement the memory access interleaving function.
Tccd, CAS to CAS Delay - minimum time between two CAS# commands.
Twr, Write Recovery, Write to Precharge - the minimum time between the end of a write operation and the command to precharge a row for one bank.
Twtr, Trd_wr, Write To Read - the minimum time between the end of writing and the issuance of a read command (CAS#) in one rank.
RTW, Read To Write, (Same) Rank Read To Write - the minimum time between the end of a read operation and the issuance of a write command, in one rank.
Same Rank Write To Write Delayed- the minimum time between two commands to record in the same rank.
Different Rank Write to Write Delay- the minimum time between two teams to record in different ranks.
Twr_rd, Different Ranks Write To READ Delayed - the minimum time between the end of writing and the issuance of a read command (CAS#) in different ranks.
Same Rank Read To Read Delayed- the minimum delay between two read commands in the same rank.
Trd_rd, Different Ranks Read To Read Delayed - minimum delay between two read commands in different ranks.
Trtp, Read to Precharge - the minimum interval between the issuance of a read command before the command to precharge.
Precharge to Precharge- minimum time between two pre-charge commands.
tpall_rp, Precharge All to Active Delay - delay between the Precharge All command and the line activation command.
Same Rank PALL to REF Delayed- sets the minimum time between Precharge All and Refresh in the same rank.
Different Rank REF to REF Delayed- sets the minimum delay between two commands to update (refresh) in different ranks.
Twcl, Write Latency - delay between the issuance of a write command and the DQS signal. Similar to CL, but for the record.
Tdal, quoted from JEDEC 79-2C, p.74: auto precharge write recovery + precharge time (Twr+Trp).
Trcd_rd/Trcd_wr, Activate to Read/Write, RAS to CAS Read/Write Delay, RAW Address to Column Address for Read/Write - combination of two timings - Trcd (RAS to CAS) and rd/wr command delay. It is the latter that explains the existence of different Trcd - for writing and reading (Nf2) and BIOS installation - Fast Ras to Cas.
Tck, Clock Cycle Time - period of one cycle. It is he who determines the frequency of memory. It is considered as follows: 1000/Tck=X Mhz (real frequency).
CS, Chip Select - the time required to execute the command given by the CS# signal to select the desired memory chip.
Tac, DQ output access time from CK - time from the front of the cycle to the output of data by the module.
Address and Command Setup Time Before Clock- the time for which the transmission of command address settings will precede the rising edge of the clock.
Address and Command Hold Time After Clock- the time for which the address and command settings will be "locked" after the falling edge of the clock.
Data Input Setup Time Before Clock, Data Input Hold Time After Clock- same as above, but for data.
Tck max, SDRAM Device Maximum Cycle Time - maximum device cycle time.
Tdqsq max, DDR SDRAM Device DQS-DQ Skew for DQS and associated DQ signals - maximum shift between DQS strobe and associated data signals.
Tqhs, DDR SDRAM Device Read Data Hold Skew Factor - maximum "lock" shift of read data.
tch, tcl, CK high/low pulse width - the duration of the high/low level of the clock frequency CK.
Thp, CK half pulse width - the duration of the half-cycle of the clock frequency CK.
Max Async Latency- maximum asynchronous delay time. The parameter controls the duration of the asynchronous delay, which depends on the time required for the signal to pass from the memory controller to the farthest memory module and back. The option exists in AMD processors (Athlon/Opteron).
DRAM Read Latch Delay- a delay that sets the time required for the "locking" (unambiguous recognition) of a particular device. Actual when the load (number of devices) on the memory controller increases.
Trepre, Read preamble - the time during which the memory controller delays the activation of data reception before reading, in order to avoid data corruption.
Trpst, Twpre, Twpst, Write preamble, read postamble, write postamble - the same for writing and after receiving data.
Read/Write Queue Bypass- specifies the number of times the earliest request in the queue can be bypassed by the memory controller before being executed.
Bypass Max- determines how many times the earliest entry in the DCQ can be bypassed before the arbitrator's choice is annulled. When set to 0, the choice of arbitrator is always taken into account.
SDRAM MA Wait State, Read Wait State - setting 0-2-cycle advancing of address information before the CS# signal is given.
Turn-Around Insertion- delay between cycles. Adds a one-tick delay between two consecutive read/write operations.
DRAM R/W Leadoff Timing, rd/wr command delay - delay before executing a read/write command. Usually 8/7 or 7/5 bars, respectively. The time from issuing a command to activating the bank.
Speculative leadoff, SDRAM Speculative Read - Usually, the memory receives the address first, then the read command. Since it takes a relatively long time to decode an address, it is possible to apply preemptive start by issuing an address and a command in succession without delay, which improves bus utilization and reduces downtime.
Twtr Same Bank, Write to Read Turnaround Time for Same Bank - the time between the termination of the write operation and the issuance of a read command in the same bank.
Tfaw, Four Active Windows - minimum time for four windows (active rows) to be active. It is used in eight-bank devices.
Strobe Latency. Delay when sending a strobe pulse (selector pulse).
Memory Refresh Rate. Memory refresh rate.
We hope that the information presented by us will help you understand the designation of memory timings, how important they are and what parameters they are responsible for.