BASICS OF MICROPROCESSOR TECHNOLOGY

Lecture notes

Moscow 2013

ORGANIZATION OF MICROPROCESSORS AND MICROPROCESSOR SYSTEMS

MICROPROCESSOR SYSTEMS BASED ON MICROPROCESSOR KIT K580 SERIES

Composition of the microprocessor kit

The K580 series MPC contains a set of LSIs for building low-speed microprocessor systems operating at a clock frequency of up to 2.5 MHz. Using this MPC, microprocessor systems (MPS) are built that solve problems of controlling various technological processes.

The kit has the following features. It provides a central processor LSI, which contains operating and control devices in one chip, which significantly simplifies the construction of a microprocessor system. In addition, to facilitate programming when controlling MPC microcircuits, a fixed set of commands is used, which leads to a decrease in the speed of the microprocessor system. This is due to the fact that the proposed set of commands may be insufficient to solve a specific problem.

A number of microcircuits included in the MPC are made using n-MOS technology, others - using TTLSh technology. However, regardless of the manufacturing technology, all input and output signals of the K580 series microcircuits correspond to the levels of TTL technology logic circuits, which simplifies coordination with TTL technology microcircuits of any series.

All MPC microcircuits can operate in the temperature range from -10° C to + 70° C. The K580VM80A microcircuit requires three voltage sources: power: +5 V, -5 V and +12 V, the K580GF24 microcircuit requires two sources: +5 V and +12 V, the rest of the microcircuits are from one source: +5 V.

Table 2.1 shows the composition of the K580 series microprocessor kit.

Table 2.1 Composition of the microprocessor kit

Chip designation	Purpose	Function performed
K580VM80A	Parallel CPU	Central processor with a fixed instruction set for processing parallel 8-bit information
K580VV51A	Universal synchronous/asynchronous transceiver	8-Bit Universal Synchronous/Asynchronous Serial Transceiver
K580VI53	8 or 16-bit timer	Generates software-controlled time delays to synchronize controlled objects in real time
K580VV55A	8-bit parallel port	Programmable I/O of parallel information
K580VT57	8 or 16-bit DMA controller	High-speed information exchange between MPS memory and peripheral devices
K580VN59	Interrupt controller	Serves up to eight interrupt requests from external devices
K580VV79	8-bit keyboard and display interface	I/O controller for keyboard and display
K580VG75	8 or 16-bit CRT interface	Controller for outputting information from the MPS memory to the cathode ray tube screen
K580VK91A	Channel interface	Device for interfacing the microprocessor with the information-measuring system
K580VA93	Channel transceiver	Transceiver microprocessor - public channel
K580GF24	Clock generator	Generates two sequences of clock pulses necessary for the operation of the central processor
K580VK28 K580VK38	System controller and bus driver	Generates control signals for various devices included in the MPS
K580IR82 K580IR83	Buffer register	8-bit tri-state buffer register
K580VA86 K580VA87	Bus former	Bidirectional, 8-bit, high-load, tri-state bus driver

Register block

The K580 microprocessor contains software-accessible 8-bit registers general purpose(RON) and 16-bit specialized registers: program counter and stack pointer register. In addition, there are registers that are not directly accessible to the program: 8-bit temporary storage registers W, Z and a 16-bit address register.

General purpose registers B, C, D, E, H, L are used to store operands, intermediate and final results, as well as addresses and indices for indirect and index addressing. To perform operations with double-length words and operations of forming and transferring double-byte addresses, it is possible to operate with the contents of register pairs BC, DE, HL.

A special feature of the MP register block is the presence in its composition increment/decrement schemes(INC/DEC), which produces over the content program counter(PC) and stack pointer register(SP) operation of adding/subtracting 1 without involving the ALU.

Program counter(16-bit register) is designed to store the command address; after sampling from random access memory of the current command, the contents of the counter are increased by one and thus the address of the next command is formed (in the absence of unconditional and conditional transitions).

Stack pointer(16-bit register) is used to address stack memory. The MP K580 uses an “inverted” stack, i.e. When a word is pushed onto the stack, the value of the stack pointer (the address of the top of the stack) is decreased, and when a word is popped from the stack, it is increased.

Stack addressing is widely used when working with subroutines and interrupt routines.

Registers are used for short-term storage of some operands and results of operations. temporary data storage W, Z. The use of temporary storage registers allows the MP to implement, for example, such an operation as exchanging the contents of two registers in one command execution cycle.

The register block includes a register memory addresses(RA), designed to store the address of the memory cell in which the current command is written. The address register is not accessible to the programmer. However, any pair of registers (BC, DE, HL) can be used to specify the addresses of instructions and data in the program.

Buffer circuits

The bidirectional data bus buffer is designed to logically and electrically separate the intraprocessor data bus from the external, system data bus. The buffer consists of a latch register and a tri-state output circuit, i.e. a circuit that provides output states of 0, 1 and complete disconnection from the load (high-impedance state).

In information input mode, the internal data bus is connected to a buffer latch register, which is loaded from the external bus by a buffer circuit under command control.

In the information output mode, the buffer circuit transmits the contents of a latch buffer register to the data bus, to the input of which the information to be output is loaded from one of the registers via the internal bus.

During the performance of operations in MP that are not related to exchange procedures with external devices The buffer circuit is disconnected from the data bus.

During the execution of operations in the MP not related to exchange procedures with system devices external to the MP, the buffer circuit is disconnected from the data bus, i.e. goes into a high-impedance state (not zero, not one).

The address bus buffer circuit is unidirectional and ensures the transfer of command and data addresses, as well as numbers of peripheral devices from the MP to the system. The output of the address buffer, just like the data buffer, can go into a disabled state.

Control device

Control block includes:

8-bit command register (RK), designed to receive and store the operation code;

Control and synchronization unit (CU), which generates control signals for all internal registers and MP blocks, as well as its output control signals;

Control memory, implemented on a programmable logic matrix, in which microprograms of individual operations are stored. The user cannot change the contents of control memory, and, consequently, the composition of commands.

Data Transfer Commands

Data transfer commands perform operations of storing, exchanging, loading and moving data. Among all the microprocessor instructions, these instructions are the most commonly used. Condition signs are not set by commands in this group. Table 2.5 shows the data transfer commands.

Table 2.5 Data transfer commands

Command mnemonic	Operation code	Number of bytes per command		Actions Performed
MOV R1, R2	01DDDSSS	1	1	(R1) (R2)
MOV R, M	01DDD110	1	2	(R)M(HL)
MOV M, R	01110SSS	1	2	M(HL) (R)
MVI R, data	00DDD110	2	2	(R) (byte2)
MVI M, data	00110110	2	3	M(HL) (byte2)
LXI RP, data	00RP0001	2	3	(RH) (byte3); (RL) (byte2).
LDA addr	00111010	3	4	(A) ((byte3)(byte2))
LHLD addr	00101010	3	5	L((byte3)(byte2)); H ((byte3)(byte2)+1).
LDAX RP	00RP1010	1	2	(A) (M)
XCHG	11101011	1	1	(H) « (D); (L) « (E)
STA addr	00110010	3	4	((byte3)(byte2)) (A)
SHLD addr	00110010	3	5	((byte3)(byte2)) (L); ((byte3)(byte2)+1) (H)
STAX RP	00RP0010	1	2	M(RP) (A)

Register-addressed transfer instruction MOV A, D) transfers the contents of register D to the accumulator. Directly addressing command MVI D, 4E 16 transfers the number given in the second byte of the command (in the example the number 4E 16) to register D, the address of which is indicated in bits 5...3 of the first byte of the command. Direct addressing command LDA 0200 16 transfers the contents of the memory cell, the address of which is indicated in the second and third bytes of the command (0200 16), to the battery. Team LDAX BC The contents of a RAM cell, the address of which is the contents of a pair of registers BC, are loaded into the accumulator.

Teams logical operations

The purpose of these commands is to perform the logical operations AND, OR, XOR, comparison, shift and invert. These instructions perform logical operations on data in memory or registers and attributes. Table 2.7 shows the commands for logical operations.

Table 2.7 Logical Operation Commands

Command mnemonic	Operation code	Number of bytes per command	Command execution time, cycles	Actions Performed
ANA R	10100SSS	1	1	(A) (A)Ù(R). The flags are set – Z, S, P, AC.
ANA M	10100110	1	2	(A) (A)ÙM(HL). The flags are set – Z, S, P, AC.
ANI data	10101SSS	2	2	(A) (A)Ù(byte2). The flags are set – Z, S, P, AC.
XRA R	10101SSS	1	1	(A) (A)Å(R). Flags are set – Z, S, P.
XRA M	10101110	1	2	(A) (A)ÅM(HL). Flags are set – Z, S, P.
XRI data	11101110	2	2	(A) (A)Å(byte2). Flags are set – Z, S, P.
ORA R	10110SS	1	1	(A) (A)Ú(R). Flags are set – Z, S, P.
ORA M	10110110	1	2	(A) (A)ÚM(HL). Flags are set – Z, S, P.
ORI data	11110110	2	2	(A) (A)Ú(byte2). Flags are set – Z, S, P.
CMP R	10111SSS	1	1	(A)-(R). Flags – Z=1 if (A)=(R), C=1 if (A)<(R).
CMP M	10111110	1	2	(A)-M(HL). Flags – Z=1 if (A)=(M), C=1 if (A)<(M).
CPI data	11111110	2	2	(A)-(byte2). Flags – Z=1 if (A)=(byte2), C=1 if (A)<(байт2).
RLC	00000111	1	1	Shift left (A) (2A). The C flag is set.
RRC	00001111	1	1	Shift right. (A) (A/2). The C flag is set.
RAL	00010111	1	1	Cyclic shift to the left. The C flag is set.
RAR	00011111	1	1	Cyclic shift to the right. The C flag is set.
CMA	00101111	1	1
CMC	00111111	1	1
STC	00110111	1	1	(C)1.

Programming Techniques

To program the MP, you need to know the composition of the instructions, be well acquainted with the purpose and location of the registers, i.e. know microprocessor architecture.

The stages of program development must be performed in the following sequence:

1. Definition and analysis of the problem;

2. Drawing up a block diagram of the solution algorithm in general form and a machine algorithm;

3. Writing a program in Assembly language;

4. Translation of the program into machine codes;

5. Debugging the program (finding and eliminating errors);

6. Documenting the program.

Let us formulate the general requirements for programs written in Assembly language.

In general, any command in Assembly language is written as follows:

Label: Operation Data; A comment

Label used to indicate the address of the memory location in which a given instruction is stored. It can be six characters long, must not include punctuation or spaces, and the first character must be a letter. The label is always specified by a colon and is an optional element of the command. It is used only when necessary.

Operation is a required element of the command. It is a mnemonic record of two to four letters that indicate the nature of the actions being performed, for example:

HLT is a mnemonic designation for the command to stop MP K580.

Data– part of a command that can contain one or two eight-bit words depending on the type of command (memory cell address, I/O port address, direct data).

6.3.3. Programming learning tasks

Let's start programming educational tasks by writing a program that reads the state of the button SB1 and displays it on the LED indicator VD2 so that the button is not pressed (high signal level at the input RA4 ) corresponds to the glowing state of the LED, and vice versa.

Listing 12.2. (html, txt)

Listing 12.2. (html, txt)

;main program

LOOP

CALL SB1_VD2 ;call subroutine SB1_VD2

;repeating the process

GET_RA ;status reading subroutine

;port A

SB1_VD2 ;LED output subroutine

;VD2 state of button SB1 (bit 4

;register TEMPA)

GOTO P0 ;go to P0

;TEMPA,4=0 (button pressed)

GOTO P1 ;go to P1

BCF VD2 ;extinguish LED

RETURN

Listing 12.2.

The main program contains a closed loop LOOP GOTO LOOP , necessary for periodically repeating the cycle of monitoring the state of the button and displaying it on the indicator. Team CLRWDT eliminates the influence of a possible reset due to watchdog timer overflow on the operation of the program. The following two commands call subroutines GET_RA and SB1_VD2. The first of them (GET_RA ) first reads the current state of the port A , which is placed in the working register W . Since the working register may be needed when executing other instructions, its status is written to the register TEMPA , used here to temporarily store port state A . Thus, after returning from the subroutine GET_RA in rank 4 registers TEMPA contains information about the state of the button SB1 : "1" not pressed, "0" pressed.

Subroutine SB1_VD2 TEMPA and, depending on it, lights up or turns off the LED. There are no conditional jump commands in the command system of the PIC16F84 microcontroller, therefore, to organize the verification of one or another condition, commands are used that allow you to skip the execution of the next program command, depending on the state of a certain bit in a given register ( BTFSS and BTFSC ). In particular, the team BTFSS TEMP,4 skips command execution GOTO P0 if TEMP,4 = 1 (button not pressed). Thus the command is implemented BSF VD2 , which lights up the LED VD2 . Then the condition is analyzed TEMP,4 = 0 (the button is pressed) and, if it occurs, the LED goes out.

A simpler implementation of the given algorithm is possible, since the pressed state of the button excludes the non-pressed state (and vice versa), but the presented option is more clear.

Let's consider a more complex version of the program, which involves lighting an LED VD2 only with the following state of the toggle switches and layout buttons: SA1 = 1, SA2 = 1, SB1 = 1 and SB2 = 0.

Listing 12.3. (html, txt)

Listing 12.3. (html, txt)

;main program

LOOP

CLRWDT ;watchdog reset

CALL GET_RA ; calling the GET_RA subroutine

CALL GET_RB ; calling the GET_RB subroutine

CALL ZAG_1110 ; call of subroutine ZAG_1110

GOTO LOOP ;go to LOOP mark for

;repeating the process

GET_RB ;status reading subroutine

;port B

MOVF PORTB,W ;read the state of port B in W

MOVWF TEMPB ;forward W to TEMPB

RETURN

ZAG_1110 ; lights up the VD2 LED only when

;the following state of the toggle switches and

;layout buttons:

;SA1 = SA2 = SB1 = 1 and SB2 = 0

BTFSS TEMPA,2 ;skip command if

GOTO P0 ;TEMPA,2=1

BTFSS TEMPA,3 ;skip command if

GOTO P0 ;TEMPA,3=1

BTFSS TEMPA,4 ;skip command if

GOTO P0 ;TEMPA,4=1

BTFSC TEMPB,0 ;skip command if

GOTO P0 ;TEMPB,0=0

BSF VD2 ;light up LED VD2

GOTO P1

BCF VD2 ;extinguish LED VD2

RETURN

INCLUDE GET_RA.ASM

Listing 12.3.

Subroutines GET_RA and GET_RB put into registers TEMPA and TEMPB current port states A and B , respectively. Subroutine ZAG_1110 analyzes the states of bits 2, 3 and 4 of the register TEMPA and bit 0 of the register TEMPB , and subject to TEMPA,2,3,4 = 1,1,1 and TEMPB,0 = 0 , lights up the LED VD2 . If at least one of these conditions is not met, the LED turns off.

Using a Directive INCLUDE GET_PORTA.ASM allows you to include already debugged subroutine modules into the current program. In order to use this feature, it is necessary to save the debugged modules as separate assembler files.

Let's now try to use a seven-segment indicator to monitor the state of the layout toggle switches. First, let's write a program that displays on the indicator H.L. seven-segment image of any binary number from 0b to 1111b in hexadecimal notation.

Listing 12.4. (html, txt)

Listing 12.4. (html, txt)

;main program

LOOP

CLRWDT ;watchdog reset

MOVLW 0x0A ;send constant 0A to W

GOTO LOOP ;go to LOOP mark for

;repeating the process

SEV_SEG ;maintenance subroutine

;seven-segment indicator

ANDLW 0x0F ;masking 4 least significant digits

;W and zeroing the 4 highest ones

ADDWF PCL,F ;add W with PCL and forward

;result in PCL

RETLW 0x80 ;return from subroutine from 80 to W

RETLW 0xF2 ;return from subroutine from F2 to W

RETLW 0x48 ;return from subroutine from 48 to W

RETLW 0x60 ;return from subroutine from 60 to W

RETLW 0x32 ;return from subroutine from 32 to W

RETLW 0x25 ;return from subroutine from 25 to W

RETLW 0x04 ;return from subroutine 04 to W

RETLW 0xF0 ;return from subroutine from F0 to W

RETLW 0x00 ;return from subroutine from 00 to W

RETLW 0x20 ;return from subroutine from 20 to W

RETLW 0x10 ;return from subroutine from 10 to W

RETLW 0x06 ;return from subroutine from 06 to W

RETLW 0x8C ;return from subroutine from 8C to W

RETLW 0x42 ;return from subroutine from 42 to W

RETLW 0x0C ;return from subroutine from 0C to W

RETLW 0x1C ;return from subroutine from 1C to W

Listing 12.4.

The program begins its work by sending a constant 0x0A to working register W . Then the seven-segment indicator maintenance subroutine is called SEV_SEG . Subroutine operation SEV_SEG starts with masking the 4 least significant digits W and resetting the 4 eldest ones to zero. Thus, the most significant bits of the data transferred from the working register are excluded from the analysis. W numbers. Then the masked register contents W added to the current state of the low byte of the program counter PCL , and the result is placed in PCL . Thus, an additional offset of the program counter is made by the amount that was transferred in the working register. For example, if there was W=0 , then the contents of the program counter will not change, and the next command will be executed RETLW 0x80 0x80 = B"1000000" to W register . If, as was the case in the given program, W=0A , then to the contents PCL number will be added 0x0A , and an additional shift of 10 steps will occur. As a result, the command will be executed RETLW 0x10 , which will cause the subroutine to return with the entry 0x10 = B"0001000" into the W register.

After returning from the subroutine, the transfer is made W to PORTB and displaying its status on a seven-segment indicator H.L. . In particular, if W = 0, then when outputting 1000000b to port B the seven-segment indicator will show 0, and when W = A it will show A .Thus, any 4-bit binary number can be displayed.

Direct program counter control method used in subroutine SEV_SEG , can be used to implement tabular conversion of numbers. Please note that this method does not allow you to convert more than 256 values ​​in one table. In addition, the table conversion program must be located entirely within a 256-byte block to avoid overflowing the low byte of the program counter.

Using a subroutine SEV_SEG , let’s now write a program that reads the states of toggle switches SA1 and SA2 and displays the corresponding number on the indicator.

Listing 12.5. (html, txt)

Listing 12.5. (html, txt)

;main program

LOOP

CLRWDT ;watchdog reset

CALL GET_RA ; calling the GET_RA subroutine

RRF TEMPA,F ;shift right one bit

;through transfer

RRF TEMPA,W ;shift right one bit

;through transfer

ANDLW 0x03 ;mask for two low-order bits

CALL SEV_SEG ; call to subroutine SEVEN_SEG

MOVWF PORTB ; forwarding W to PORTB

GOTO LOOP ;go to LOOP mark for

;repeating the process

INCLUDE GET_RA.ASM

INCLUDE SEV_SEG.ASM

Listing 12.5.

Subroutine GET_RA puts into register TEMPA current port status A . Thus, in bits 2 and 3 of the register TEMPA the current state of the toggle switches is stored SA1 and SA2 . In order for the status bits of the toggle switches to occupy positions 0 and 1 of the register TEMPA , two shifts to the right are performed via carry, and the result of the second shift is placed in the register W . Then a mask is applied to the two low-order digits of the working register and the subroutine is called SEV_SEG . After exiting the subroutine, the result is sent to the port B and is displayed on the indicator.

Let us now consider programs that operate in real time, i.e. producing signals of a certain duration and repetition rate, or taking into account the timing parameters of input signals. The main element of such programs is the subroutine for generating a time delay. Let's consider one of the possible options for such a subroutine using software methods for generating a delay, i.e. without using the built-in timer.

Listing 12.6. (html, txt)

Listing 12.6. (html, txt)

;main program

MOVLW 0xL ;sending constant H"L" to W

CALL DELAY ;call subroutine DELAY

DELAY ;formation subroutine

;time delay

LOOPD

RETURN ;return from subroutine

Listing 12.6.

The main program calls a subroutine DELAY with some constant L in working register W , which determines the number of internal loops of the subroutine. Subroutine DELAY begins its work by loading the contents of the working register into the user register COUNT1. Command DECFSZ COUNT1,F Decrements the contents of the register by one COUNT1 and checks it for equality to zero. Register zero state COUNT1 causes the loop to exit and return from the subroutine. To execute each internal cycle, three MC machine cycles are required (1 cycle per command execution DECFZ with a non-zero result and 2 cycles for each command GOTO ). Exiting a subroutine DELAY will require 4 cycles (2 cycles to execute the command DECFZ with zero result and 2 cycles for RETURN ). If we add to this another 4 cycles required to load the constant into the working register, call the subroutine and load the user register COUNT1 , then the total execution time of the subroutine DELAY (delay) will be

TD = 4 + 3*(L 1) + 4 = 5 + 3*L cycles,

where L constant passed through the working register to the subroutine DELAY.

L = H"00" = .0 the maximum generated time interval will be 1.55 ms. This result is due to the fact that the team DECFZ first decrements the contents of the register ( H"00" 1 = H"FF" ), and then analyzes the result.

The minimum generated time interval will be 5 cycles or 10 μs under the same conditions. To obtain such an interval, before calling the subroutine, DELAY load a number into the working register 0x01 .

To expand the upper limit of the generated time intervals, as well as to improve the convenience of working with the subroutine, you can add to the loop LOOPD one or more additional commands, the most commonly used command being NOP . For example, consider the subroutine for generating a time delay DELAY_C

Listing 12.7. (html, txt)

Listing 12.7. (html, txt)

DELAY_C ;formation subroutine

;time delay (option C)

LOOPD

NOP ;empty command

GOTO LOOPD ;repeat the loop H"L" times

RETURN ;return from subroutine

Listing 12.7.

Total execution time of the subroutine DELAY_C , including her call, will be

TD = 4 + 4*(L 1) + 4 = 4 + 4*L cycles.

At clock frequency fosc = 2 MHz and constant loading L = H'F9' = .249 the generated time interval will be exactly 2 ms. Decreasing the constant by one reduces the generated time interval by 8 μs. In particular, when L=.124 a delay of 1 ms is created.

For the formation of large time delays, lying in the range of fractions and units of seconds, this approach is inconvenient. In this case, nested loops are used, as shown in the following example.

Listing 12.8. (html, txt)

Listing 12.8. (html, txt)

;main program

MOVLW 0xL ;send constant H'L' to W

CALL DELAY_D ;call subroutine DELAY_D

DELAY_D ;formation subroutine

;long time delay (option D)

LOOPD

CLRWDT ;watchdog reset

RETURN ;return from subroutine

Listing 12.8.

DELAY_D is 3*256 + 4

TD = 5 + (3*256 + 4)*L cycles.

At a clock frequency fosc = 2 MHz, the cycle time is tc = 2 μs, so when loading L = H'00' = .0 the maximum generated time interval will be about 0.4 s.

Since the generated time interval is quite large, a command to reset the watchdog timer is included in the outer loop.

A time interval of 0.4 s is not entirely convenient for obtaining time delays that are multiples of a second, so let’s consider another version of the subroutine for generating large time delays with an additional command NOP in the inner loop.

Listing 12.9. (html, txt)

Listing 12.9. (html, txt)

DELAY_E ;formation subroutine

;long time delay (option E)

CLRF COUNT1 ;reset the contents of the COUNT1 register

LOOPD

NOP ;empty command

GOTO LOOPD ;repeat the loop 256 times

CLRWDT ;watchdog reset

GOTO LOOPD ;repeat the loop H'L' times

RETURN ;return from subroutine

Listing 12.9.

Execution time of the inner loop of the subroutine DELAY_E is 4*256 + 4 machine cycles of the MK, so the total delay will be

TD = 5 + (4*256 + 4)*L cycles.

At clock frequency fosc = 2MHz and at boot L = H'F3' = .243 the generated time interval will be about 0.5 s with an error of no more than 0.2%. If higher precision is required, the required number of empty operations can be inserted into the outer delay generation loop.

Let us next consider several programs using subroutines for generating time delays. Let's start by writing a program that sends a beep to the speaker BA1 when you press a button SB1 . The speaker will only sound if the output RA0 a periodically changing signal will be given. In order for a sound to be clearly heard, its frequency must be close to the maximum audibility of the human ear. Let's choose a sound frequency equal to 1 KHz, which corresponds to a signal pulse repetition period of 1 ms.

Listing 12.10. (html, txt)

Listing 12.10. (html, txt)

;main program

LOOP

CLRWDT ;watchdog reset

CALL GET_RA ;subroutine call GET_PORTA

CALL SB1_BA1 ;call subroutine SB1_BA1

GOTO LOOP ;go to LOOP mark for

;repeating the process

SB1_BA1 ;subroutine for supplying sound to

;speaker BA1 when pressing the button

;SB1

BTFSC TEMPA,4 ;skip command if

;TEMPA,4=0 (button pressed)

GOTO B0 ;go to B0

BSF BA1 ;high level supply to RA0

;H'3E' = .62 in W

BCF BA1 ;low level supply to RA0

MOVLW 0x3E ;send constant

;H'3E' = .62 in W

CALL DELAY_C ;call subroutine DELAY_C

RETURN

INCLUDE GET_RA.ASM

INCLUDE DELAY_C.ASM

Listing 12.10.

As before, the subroutine GET_RA reads the current state of port A, which is then passed into the register TEMPA. Subroutine SB1_BA1 analyzes the state of bit 4 of the register TEMPA and, depending on the result, the speaker speaks BA1 or not. Required line speed RA0 in single and zero states is provided by the subroutine DELAY_C with parameter L = H'3E' = .62 . This corresponds to a delay time of about 0.5 ms, which results in the required signal repetition rate of 1 kHz.

Next, consider a program that makes the LED blink VD2 when you press a button SB1 . In order for the blinking to be clearly visible, we select its frequency to be 1 Hz.

Listing 12.11. (html, txt)

Listing 12.11. (html, txt)

;main program

LOOP

CLRWDT ;watchdog reset

CALL GET_RA ; calling the GET_RA subroutine

CALL SB1_VD2M ;subroutine call

;SB1_VD2M

GOTO LOOP ;go to LOOP mark for

;repeating the process

SB1_VD2M ;LED blinking subroutine

;VD2 when pressing the SB1 button

BTFSC TEMPA,4 ;skip command if

;TEMPA,4=0 (button pressed)

GOTO V0 ;go to V0

BSF VD2 ;light up LED VD2

;H'F3' = .243 in W

BCF VD2 ;extinguish LED

MOVLW 0xF3 ;send constant

;H'F3' = .243 in W

CALL DELAY_E ;call subroutine DELAY_E

BTFSS TEMPA,4 ;skip command if

;TEMPA,4=1 (button not pressed)

GOTO V1 ;go to V1

BCF VD2 ;extinguish LED

RETURN

INCLUDE GET_RA.ASM

INCLUDE DELAY_E.ASM

Listing 12.11.

The program works almost the same as the previous one. The first difference is that the LED is forcibly extinguished when the button is not pressed. The second difference is the size of the time interval, which here is 0.5 s and is formed by the subroutine DELAY_E .

Time delay routines can also be useful when working with external signal sources such as toggle switches, buttons, switches, etc. The fact is that all mechanical switches have one negative property, known as contact “bouncing,” which is caused by mechanical vibrations of the contacts when they close and open. The duration of the oscillations is usually several milliseconds, during which a burst of pulses can be received at the input of the MC instead of an ideal drop.

Hardware methods of dealing with contact bounce are based on the use of RS flip-flops, monostables or Schmitt triggers. In MCU-based devices, contact bounce suppression is usually carried out by software methods, which are based on re-reading the state of the port line after a certain time.

As an example, consider the “bounce-free” version of the subroutine for reading the port state A.

Listing 12.12. (html, txt)

Listing 12.12. (html, txt)

GET_RAD ;status reading subroutine

;port A to TEMPA register

;with suppression of "rattling"

MOVF PORTA,W ;read the state of port A in W

ANDLW 0x1C ;mask overlay b'00011100'

;to unused bits W

MOVWF TEMPA ;send W to TEMPA

CLRWDT ;reset watchdog timer WDT

MOVLW 0x0A ;send constant

;H'0A' = .10 in W

CALL DELAY_E ; calling the DELAY_E subroutine

MOVF PORTA,W ;read the state of port A in W

ANDLW 0x1C ;overlay mask b'00011100' on W

SUBWF TEMPA,W ;subtract W from TEMPA

BTFSS Z ;skip command if result

;null

GOTO DD ;go to DD label

RETURN

INCLUDE DELAY_E.ASM

Listing 12.12.

The essence of the subroutine is to re-read the port state A some time after the previous one and comparing it with the previous value. Constant H'0A' = .10 , sent to the register W before calling the subroutine DELAY_E , provides a time delay value of about 20 ms - this is usually sufficient to complete transient processes when switching mechanical switches. Masking unused port bits improves the reliability of the routine. Resetting the watchdog timer before calling the delay subroutine is necessary to prevent the MCU from being reset between two port polling procedures A.

Let us now consider the operation of a program that uses some of the previously developed subroutines. Let the goal of the program be to count the number of clicks on a button SB1 with the result displayed on a seven-segment indicator in hexadecimal code.

Listing 12.13. (html, txt)

Listing 12.13. (html, txt)

;main program

CLRF COUNT3 ;reset keystroke counter

LOOP

CLRWDT ;watchdog reset

CALL GET_RAD ;call subroutine GET_RAD

BTFSC TEMPA,4 ;pressure test SB1

GOTO LOOP ;if is not pressed return

;to the LOOP label

INCF COUNT3,F ;counter increment

MOVF COUNT3,W ;forwarding contents

;counter to working register

CALL SEV_SEG ;call subroutine SEV_SEG

MOVWF PORTB ;forward W to PORTB

TEST

CALL GET_RAD ; calling the GET_RAD subroutine

BTFSS TEMPA,4 ;pressure test SB1

GOTO TEST ;if is still pressed return

;to the TEST label

GOTO LOOP ;return to LOOP mark

INCLUDE GET_RAD.ASM

INCLUDE SEV_SEG.ASM

Listing 12.13.

The programs presented in the chapter do not cover even a small fraction of the possibilities that even such a simple layout as shown in rice. 6.3 . However, mastering them, I hope, will be useful for novice users of PIC controllers.

Communication, communication, radio electronics and digital devices

An MP microprocessor is a processing and control device capable of performing information processing, decision making, input and output of information under program control, and made in the form of one or more LSIs. used for temporary storage of information during the operation of the MP. Unlike ROM, RAM can both read and write information using the Read and Write signals into a cell whose address is located on SHA. By signal Vv input to the control cabinet, information is transferred from an external device to the SD, and by signal output output...

Lecture 12

Microprocessor technology

1 Microprocessors and microprocessor kits

1.1 Microprocessor definition

In the early 70s, advances in technology in microelectronics led to the creation of a new electronics element base - microelectronic large-scale integrated circuits (LSI) (module 1 chapter 1.6.3). According to the degree of integration (the number of active elements: diodes and transistors), integrated circuits (ICs) are conventionally divided into ICs with a low degree of integration - up to 100 active elements, medium degree of integration (SIS) - up to 1000 active elements, LSI - over 1000 active elements, VLSI - over 10,000 elements. The release of a new LSI at the current level of design automation is a very complex and expensive process due to the large initial costs of developing its logical structure and topology, manufacturing photomasks and technological preparation for production. This is 0.5-1 year of work for a large team. Therefore, the production of LSIs is economically justified when their production amounts to tens to hundreds of thousands of units per year. It is practically impossible to produce specialized LSIs for each specific application. As a result of the search for areas of mass application of microcircuits with a high level of integration, their developers proposed the idea of ​​​​creating one universal LSI or a certain set of LSIs, the specialization of which for each specific application is achieved not by circuitry, but by software. This is how standard universal elements appeared - microprocessor LSIs with a structure similar to that of a computer.

Microprocessor (MP)this is a processing and control device capable of performing information processing, decision making, input and output of information under program control and made in the form of one or more LSIs.

1.2 Manufacturing technology of MP LSI

There are two types of LSI manufacturing technology: bipolar - based on the use of bipolar transistors and MOS (metal-oxide-semiconductor) - technology based on the use of field-effect transistors.

LSIs manufactured using bipolar technology differ in their schematic implementation methods. Transistor-transistor logic with Schottky diodes (TTLS) and emitter-coupled logic (ECL) are mainly used. TTLSH logic uses bipolar npn transistors supplemented with Schottky diodes (DS). The DS is a rectifying contact at the Al-nSi metal-semiconductor interface. In metal and silicon, the majority carriers are the same type - electrons, and there are no minority carriers. DS open at U=0.1-0.3 V and have a steep current-voltage characteristic. They are connected in parallel to the collector junction of the n-p-n transistor and form a Schottky transistor, manufactured in a single technological process. The use of DS significantly increases the performance of the transistor, since saturation of the collector junction is eliminated and there is no resorption of charges in it.

In MOS technology (module 1 chapter 1.5.5) we can distinguish 3 circuitry methods for implementing LSIs: MOS with channel conductivity p- or n-type (p-MOS or n -MOS) and complementary MOS technology (CMOS). CMOS technology uses pairs of MOS transistors n-type and p -type, connected in series (Fig. 1-1). For any signal at the input, one of the transistors is open, the other is closed. Therefore, the current flowing through the circuit is very small. CMOS LSIs have the lowest power consumption compared to other types.

Using MOS technology, the first MP LSIs (r-MOS) were manufactured in 1971. They use control R -channel, where the main charge carriers are holes. Therefore, the speed of the LSI is relatively low. Later, n-MOS and CMOS LSIs appeared, which are still widely used today.

ESL logic is based on the use of a differential amplifier on two transistors with connected emitters (Fig. 1-2.). It provides the fastest performance, but consumes the most power.

Basic data for some MP LSIs are given in table.1

1.3 Structure of microprocessor systems

The entire variety of MPS is based on the use of two types of MP:

a) single-chip MPs with a fixed word width and a fixed command system (with rigid control);

B) multi-chip (sectional) MPs with variable word width and microprogram control.

Let us consider the features of their structure.

1.3.1 MPS structure based on MP with strict control

Fig.1-3

Communication of individual elements of the MPS with each other and with external devices is carried out using three buses. Each bus is a highway consisting of several (8-16) lines.

ША - address bus, through which the addresses of memory cells and external devices are transmitted;

SD - data bus through which information is entered into or output from the MP;

SHU is a control bus through which control signals are transmitted to ensure the normal functioning of the MPS;

MP is the central element that controls the functioning of all other elements; addresses all other elements of the system, setting their address on the SHA;

G - clock pulse generator synchronizing the operation of the MP;

ROM is a read-only memory device (module 2 chapter 9.1), which stores the commands of the program executed by the MP and the constants necessary for operation. The address of the memory cell in which the required command or constant is stored is received via the ShA, and by the Read (read) signal from the MP, the information stored in this cell appears on the ShD;

RAM is a random access memory device (module 2 chapter 9.2) used for temporary storage of information during the operation of the MP. Unlike ROM, in RAM it is possible to both read and write information (using the Read and Write signals) into a cell whose address is located on SHA. In the simplest MPS, RAM may be absent, and its role is played by the internal general purpose registers (GPR) of the MP;

IU is an interface device (communication device) that coordinates the operation of the MPS and external devices, taking into account differences in their operating speeds and signal levels. Using the signal Вв (input) to the control unit, information is transferred from an external device to the SD, and using the signal Вв (output) - in the opposite direction. The data bus is common to all elements of the MPS, but the system elements should not interfere with each other. Therefore, the output of each of them is connected to the motor via a so-called 3-state circuit. It can be not only in active states (“0” or “1”), which is necessary for transmitting information, but also in a third state, in which the element is practically disconnected from the common bus. The transfer from the third state to the active one is carried out by MP control signals. At each moment of time, only one element transmitting information is connected to the common SD, and a “conflict” on the SD is eliminated. If necessary, several elements can receive information from the SD at once. This organization of MPS with the help of a common SD is forced and is due to the fact that the number of pins of LSI packages is limited, and the same pins are used for several purposes.

1.3.2 Structure of the MPS based on MP with microprogram control

The tightly controlled MP is assembled from n separate LSI sections of the central processing element CPE, each of which processes 2 (4, 8, 16) bits of data. This results in a central processor having 2n (or 4n, 8n, 16n) bits. The CPE performs the simplest actions - micro-operations when orders - micro-commands (MC) - are submitted to the control inputs. To execute commands similar to MP commands with rigid control, up to 10-15 microoperations and the same number of microcommands are required. The organization of commands from available micro-commands is left to the user.

The main advantage of microprogram-controlled MPs when they appeared was the high speed of information processing, which made it possible to manage and control very fast processes, for example, nuclear reactions. Currently, their role has significantly decreased, since modern multi-bit MPs with tight control and high clock speeds make it possible to process information even faster.

2 Microprocessor

2.1 Structure of MP K580VM80

The LSI under consideration is a single-chip MP based on n-MOS technology. Designed for building computing devices, controllers, microcomputers. MP bit size - 8 bits, clock frequency 2 MHz, command execution time 2-9 μs, supply voltage +12, +5 and -5 V, power consumption 0.75 W. The figure shows its block diagram.

2.1.1 Basic elements of MP

Information is exchanged through an eight-bit buffer register (module 2 chapter 7) of the DB, connected to the external and internal SD MP.RK - command register. The command code is written into it and stored during its execution. DshK is a command decoder that outputs signals to the control device CU and the SVR register selection circuit.

SVR - register selection scheme. Contains: 6 software-accessible general purpose registers (RON) B, C, D, E, H, L (there are commands in which they are considered in pairs B- B, C; D - D, E; H - H, L); 2 programmatically inaccessible registers W and Z, designed to store the second and third bytes of the command (the first byte is always stored in the RK);

M multiplexer (module 2 chapter 5.2), connecting the internal SD with registers W, Z;

PS - 16-bit program counter, allowing the MP to execute programs containing up to 216 = 65536 words;

US - 16-bit stack pointer (chapter 2.1.3);

LED - increment-decrement circuit (adding or subtracting 1);

BA - 16-bit address buffer;

A - result register (accumulator);

ALU is an arithmetic-logical device that performs arithmetic operations of addition - subtraction, increment - decrement, logical operations of conjunction, disjunction, inversion and others. It is connected through buffer registers BR1 and BR2 with the battery and the internal data bus;

RP - a register of signs in which, during the execution of a command, signs of the result appear (zero result, positive or negative, even or odd result), used in subsequent commands, for example, a conditional jump;

SDK - decimal correction scheme, used in the case when information is processed not in binary, but in binary decimal code (module 2 chapter 3.2);

CU is a control device that provides control over the operation of the MP and external devices. Let's consider its operation and the composition of the control bus.

2.1.2 Control device

The control device is clocked from an external generator that generates a sequence of pulses F1 and F2. It is connected to the rest of the MP by internal control signals US and feature signals Pi. The control unit is connected to the external environment by a control bus containing 10 lines (4 signals come from outside and 6 signals are issued by the MP).

Composition of the control bus.

1. Initial installation (reset). When a “1” is applied to this input, the PS is reset to 0 and program execution begins all over again.

2. Synchronization. The “1” signal at this output is generated at the beginning of each MP operation cycle (before each MP access to any external element).

3. Reading. Signal “1” indicates that the MP is ready to receive information via SD from the outside. This signal is usually connected to the “read” input of the memory and input devices.

4. /Salary The “0” signal indicates that the MP has put information on the data bus to be written to RAM or output to output devices.

5. Ready. The “1” signal at this input indicates to the MP the end of the read or write cycle. It is produced by external devices at the end of their operating cycle. If the “1” signal is not received, then the MP enters a waiting state, during which the MP holds the address on the ShA, the control signal “read” or “write” and keeps the information transmission circuits through the DB open. The waiting state is maintained until the arrival of “1” - “ready”. In the case when all external elements operate at MP speed or higher, “1” is constantly connected to the “ready” input.

6. Waiting. The “1” signal at this output indicates that the MP is in a standby state. This signal helps to identify the faulty unit that caused the MP to stop.

7. Z.Pr. - interrupt request input (chapter 7.2.7). The “1” signal comes from outside if it is necessary to interrupt the operation of the MP.

8. R.Pr. - interrupt enable. A 1 on this output indicates that interrupts are enabled. Interrupts are enabled and disabled using special commands.

9. Capture. When a “1” signal is received, the MP stops operation, the BA and DB are transferred to the third state. In this case, the MP is disconnected from the ShA and ShD.

10. Capture confirmation. The "1" signal indicates that the MP is in a capture state.

2.1.3 Store memory - stack

When accessing RAM memory cells in an MPS with a K580VM80 processor, long three-byte commands are required. The first byte contains the access command itself, and the second and third bytes indicate the address of the memory cell. Such a command takes a relatively long time to execute, and with frequent memory accesses, the operation of the MPS slows down significantly. To speed up the operation of the MPS, a memory store - a stack - is used. It works on the principle: the number written last is read first. The order of accessing the stack is strict, but there is no need to specify the address, and the access time is significantly reduced. The stack is very convenient for storing intermediate information in the event of an interruption. Its second purpose is to ensure work with programs. When moving to a subroutine, the contents of the RON are sent to the stack; after executing the subroutine, they are called from the stack to the RON. The stack can be autonomous (built into the MP) and external (located in RAM). The K580VM80 MP uses an external stack, and the chip houses a special register - the stack pointer (ST), which stores the address of the first free stack cell. The stack is usually allocated to the most senior RAM memory cells. First, the address 111 ... 1 is set, when writing, the address is decremented (A-1), when reading, it is incremented (A+1). When working with the stack, the contents of the MS are output to the SHA; when working with the main memory, the contents of the PA are output. 2.2

2.2 Functioning of MP as part of the Ministry of Railways

2.2.1 Command execution algorithm

When executing any command, the MP operation cycle always begins with the selection of the first byte of the command - the operation code (OPC) into the command register (Chapter 2.1.1). In this case, the command address from the PS is sent through the BA to the SH, the CU generates a read signal, and the COP is sent through the DB to the RC. DshK analyzes the COP and, if required, the MP selects the 2nd and 3rd bytes of the command into the W and Z registers, respectively. The address of the subsequent command byte is formed in the PS by increasing its contents by 1 using the LED. Then the command is executed. At the end, the presence of interrupt requests (ZPr signal) is analyzed. If there is such a request, the state of the PS is remembered and a transition to the interrupt processing program occurs.

2.2.2 Time diagram of MP operation

The operation of the MP occurs under the influence of two non-overlapping sequences of clock pulses F1 and F2 (Fig. 2-2).

Most information transformations are carried out by MP using F2. The time interval during which one micro-operation is performed is called a machine cycle (denoted T1, T2, etc.). A machine cycle (MC) is a sequence of clock cycles during which information is exchanged between the MP and an element external to it (denoted M1, M2, etc.). The MC contains 3-5 measures. The command is executed in 1-5 MC. Figure 2-3 conventionally shows the sequence of execution of three commands containing different numbers of MCs. In the M1 cycle, the first byte of the instruction is always fetched. Most MPs are clocked digital circuits operating under the influence of a clock pulse generator (GTI). MP K580VM80 is clocked by the GTI, generating two sequences of non-overlapping pulses F1 and F2 with a period Tclock = 0.5 - 2 μs.

2.2.3 MP status word

SD MP is not used in T1 and the beginning of T2 for receiving and issuing basic information. The MP provides circuits that ensure that an eight-bit status word (SS) is output to the SD at this time. These 8 features can be used by external elements and, in general, make it possible to simplify the organization of the MPS. The status word is issued at the beginning of each cycle in clock T2 during the F1 pulse (Fig. 2-4). Signs of SS characterize only this MC. The SS is allocated using the RS state register (Fig. 2-5), into which information from the SD is recorded at the moment t, at which the F1 and “Sync” pulses are simultaneously present. MP K580VM80 has ten types of MC and, accordingly, 10 CC, identifying these cycles. Table 2 shows the SS corresponding to all types of MCs.

Fig.2-4

Fig.2-5

Table 2 Status words of MP K580VM80

Here:

MEMR - memory reading;

INP - input command sign (generated in MC3);

M1 - sign MC1 (CP is being sampled, command execution is beginning);

OUT is a sign of an input command, generated in MC3. Similar to the /Zp MP signal, but appears somewhat earlier and remains in the RS until the end of the cycle;

HLTA - stop confirmation;

STACK - a sign of working with the stack, generated when accessing the memory using commands to work with the stack, which allows you to have 216 RAM cells and 216 stack cells;

/WO - sign of recording or output;

INTA is a sign of the start of work in interrupt mode.

For example, in the output command, CC No. 1,2,7 are issued in three MCs. The use of SS allows for better organization of management of the Ministry of Railways. To work with external devices, the MP has only 2 control signals Rt and /Zp, which do not distinguish between ROM, RAM and other external devices. Therefore, it is necessary to use some ShA bits to indicate a specific object. In the CC, the MEMR signal allows the memory to be separated from other devices, which simplifies the organization of the interconnection of individual parts of the MPS.

3 Storage devices

A storage device, or memory for short, is used to store digital information.

The MPS memory is divided into:

program memory, designed for storing programs and usually implemented in the form of read-only memory (ROM);

data memory, or random access memory (RAM) (module 2 chapter 9);

external memory for storing large amounts of information, usually implemented in the form of a magnetic disk drive (hard drive).

Most often, semiconductor ROM and RAM are used in MPS. They have such advantages as high speed, low energy consumption, high reliability, low cost, and electrical compatibility with other MPS components. The main disadvantage of semiconductor RAM is its volatility. It does not save information when the power is turned off. When this is not acceptable RAM is backed up by batteries or accumulators, but this adds complexity and cost to the system.

Functionally, memory consists of cells of the same type (registers) designed to store one word. Each cell is assigned an address, represented by a binary code.

The capacity of a memory IC is usually expressed in bits or bytes—t, 1024 bytes (or 1Kbyte), 4K bits, etc. The information organization (or format) of memory is determined by the product of m (words) x n (word length). For example, an IC with a capacity of 1024 bits may have an organization of 1024x1 (1Kx1), 256x4, 128x8. The length of memory words (nmemory) is usually chosen equal to the word length (bit capacity) of the central processor MPS ncp. If nmemory< nцп, то применяется несколько корпусов ИС. Например, с помощью 2-х ИС памяти 256х4 можно организовать ЗУ с форматом 256х8.

Memory can perform two operations: entering information into the addressable cell - record (Zp); and outputting information from the addressed cell - reading or reading (Rt). Both operations are collectively called access or, in other words, memory access.

3.1 Permanent memory

If the memory in a running system performs only read operations, then it is called read-only memory or ROM. Writing information to ROM can be done in different ways. ROM crystals programmed with a mask (ROM-PM) are written only once during the manufacturing process using a special mask (photo template). It is not possible to change the stored information. ROM-PM have high reliability and speed, high packaging density, and energy independence. Their cost in mass production is low. They are used to store unchanging programs and various constants.

If a user writes to memory once using a special device - a programmer, and then it works only for reading, then such memory is called user-programmable ROM (ROM-PP). They are used for prototyping and debugging of MPS, as well as for production in small batches.

Reprogrammable ROMs (PROMs) are also used. The user can write information to them repeatedly using a programmer, but in a running system they only perform a read operation. Information in EPROMs can be erased, and then new information can be written to them. Erasing is carried out by removing the IC from the system and is performed either by electrical pulses with an amplitude of 30-50 V, or using ultraviolet radiation. PROMs are more expensive than ROM-PM and ROM-PP and have a lower packing density.

Let's take a closer look at the internal structure of the PP ROM using the example of the simplest IC K155RE3 (Fig. 3-1), which has a 32x8 organization. To address 32 words, there are 5 address inputs A0...A4 (since 25=32). The stored word of 8 bits is formed by a multi-emitter transistor, in each emitter circuit of which there is a fusible link made of nichrome with a thickness of 200 Angstroms. When the address decoder selects a specific word, one of the multi-emitter transistors opens. If there is a jumper on the corresponding bit line, a high voltage level is established and the output transistor VT2 also opens, and the potential of output 1 is close to zero (logical “0”). If the jumper is melted, then the corresponding bit line is not connected anywhere (“floating”) and transistor VT2 is closed (logical “1”). The ROM outputs of the PP are open-collector circuits. For normal operation, they must be connected to the +Ek power supply through resistors Rн (shown with a dotted line in the figure).

In an unprogrammed IC, all jumpers are intact, transistors VT2 are open in all words, and the outputs have logical “0” levels. To program a certain bit (the state of which must be changed from “0” to “1”), signals of the desired address are sent to line A0...A4 and a high level appears on the basis of the selected multi-emitter transistor. An external circuit sets a voltage of about 8 V at the output of the programmable bit. This voltage is sufficient to turn on the zener diode VD1 with a threshold of about 7 V, which turns on the transistor VT1, and the first terminal of the jumper is grounded. Then the supply voltage of the multi-emitter transistors increases to 12 V, and then a voltage of about 5 V is applied between the terminals of the jumper. The resulting current heats and melts the jumper.

In PP ROM of this type, failures are sometimes possible due to repeated short circuits of damaged jumpers. The gap is very narrow and sometimes “swims”. To increase reliability, programmed ROMs are kept in a thermostat for 24 hours at a temperature of 100oC and the recorded information is re-checked. If “swimming” of the jumpers is detected (some recorded “1” turned into “0”), then they are burned again.

In practice, EPROMs erased by ultraviolet irradiation are widely used. They are built on MOS transistors, which differ from conventional ones in that another “floating” gate is placed between the gate and the semiconductor (substrate), completely insulated on all sides by silicon oxide. If, when recording information, a positive voltage of about 25 V and a duration of several tens of milliseconds is applied to the gates of such transistors, then under its influence the electrons, moving towards the main gate, settle on the floating gate. When reading, a positive voltage of no more than 5 V is applied to the gate. If there are no electrons on the floating gate, then the source-drain channel becomes conductive, which corresponds to the storage of a logic one. If there are electrons on the floating gate, then they shield the gate with their charge and the source-drain gap remains non-conducting, which corresponds to storing a logical “0”. Since the floating gate is surrounded by an insulating layer, electrons entering the floating gate region cannot leave it. In reality, there is electron leakage, which leads to a gradual loss of information. According to a number of companies, this time is at least 10 years.

Information is erased by ultraviolet irradiation for several tens of minutes in all elements at once. In this case, electrons are excited by radiation and flow into the substrate. As a result, all floating gates are freed from electrons, that is, a logical “1” is written to all elements.

Such PROMs include the widely used IC K573RF2 (RF4, RF5, etc.).

3.2 RAM

Random access memory or random access memory (RAM) (Module 2 Chapter 9.2) is used to store operational information required during processing. RAM, unlike ROM, allows you to: both enter information into the addressable cell (Rp operation) and output it (Rt operation). Since any addressable cell can be accessed in any order, such memories are called random access storage devices (RAMS). ). Various ways of exchanging information between RAM and MP are possible. The most commonly used memory devices are random access memories, which allow access to any address in any order. There are static and dynamic RAM.

Static RAM is implemented using direct-coupled flip-flops, which, when powered on, can store information indefinitely without additional control signals.

Most RAMs are made on the basis of MOS transistors and have a so-called matrix organization. The functional diagram of the RAM 256x1 with a 16x16 matrix organization is shown in Figure (3-2). After decoding the low-order bits of the address A0-A3, a signal Xi appears, connecting the i-th row of the matrix. The column of the matrix Yj is selected by the decoder of the most significant bits of the address A4-A7 and the memory element EPij is connected to the information output or input circuit depending on the value of the signal Sch//Zp. When Sch//Zp=1, information is read from memory; when Sch//Zp=0 - recording in memory. The VM enable signal (chip selection) activates this IC. When the VM signal is inhibited, the matrix is ​​isolated from the outputs of the decoder and the I/O bus.

Static RAM can be built on various types of semiconductor devices. Currently, the most common static memory ICs are MOS transistors. The CMOS memory element consists of 5 transistors, four of which (VT1-VT4) form a trigger. The trigger for writing and reading is controlled using a key - transistor VT5 (Fig. 3-3).

3.3 Connecting the memory to the data bus

Since the data bus (DB) is common to many devices, a “conflict” is inevitable when they operate simultaneously. It is necessary that at each moment of time only one device is connected to the SD - a source of information. Several information receivers can be connected simultaneously. It is only important that the output power of the source of information signals is sufficient to connect several receivers. Operational connection and connection of the output of any device is carried out using an output circuit that has 3 possible states: 1, 0 and “disabled”. The output of any TTL IC can be simply represented as two transistors connected in series (see Fig. 3-4).

If transistor VT1 is open and VT2 is closed, then the output signal level is high (“1”). If on the contrary: VT2 is open, VT1 is closed, then the output is low level (“0”). If both transistors are turned off at the same time, the output of the IC is disconnected from the power source and does not have any effect on the operation of other devices connected to the common bus.

Fig.3-4 Tri-state output

4. Interface devices

Interface devices (ID) are used to interface external devices with the MPS. They are usually implemented in the form of one or more SIS or LSI.

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	INSTITUTE OF THE COMMISSIONER FOR HUMAN RIGHTS IN THE RF In the Russian Federation, the Commissioner for Human Rights in the Russian Federation is responsible for protecting the rights and freedoms of citizens and their observance by state authorities, local governments and officials. Within the limits of its competence, the Commissioner for Human Rights in the Russian Federation: 1 considers complaints from citizens of the Russian Federation and foreign citizens and stateless persons located on the territory of the Russian Federation; 2 considers complaints against decisions or actions of state bodies, local government officials...
45332.		State Duma of the Russian Federation - chamber of the Federal Assembly of the Russian Federation	26.28 KB
	The powers of local self-government are the rights and responsibilities assigned to the population of the relevant territories by elected and other local government bodies, assigned by federal legislation as well as regulatory legal acts of the constituent entities of the Russian Federation and legal acts of local self-government bodies related to the implementation of the tasks and functions of local self-government in the relevant territory. The powers of local self-government are exercised directly by the population of urban and rural settlements of other territories through...
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	Constitutional and legal status of a member of the Federation Council and a deputy of the State Duma The constitutional and legal status of a member of the Federation Council and a deputy of the State Duma is determined by the Constitution of the Russian Federation, Art. On the status of a member of the Federation Council and a deputy of the State Duma of the Federal Assembly of the Russian Federation. A deputy of the State Duma is an elected representative of the people authorized to exercise legislative and other powers in the State Duma provided for by the Constitution of the Russian Federation and federal law. Term of office...
45334.		System of legislative (representative) and executive bodies of state power of the constituent entities of the Russian Federation	20.8 KB
	The system of legislative representative and executive bodies of state power of the constituent entities of the Russian Federation is established by them independently in accordance with the fundamentals of the constitutional system of the Russian Federation and the Federal Law of 06. On the general principles of the organization of legislative representative and executive bodies of state power of the constituent entities of the Russian Federation. Education formation of the activities of legislative representative and executive bodies state authorities of the constituent entities of the Russian Federation their...
45335.		Legislative process in the Russian Federation	25.93 KB
	An urban settlement may also contain rural settlements that do not have the status of rural settlements in which local self-government is exercised by the population directly and or through elected and other local government bodies. Urban district is an urban settlement that is not part of a municipal district and whose local government bodies exercise powers to resolve statutory issues of local significance of the settlement and issues of local significance of the municipal district and can also...
45336.		Approaches to building artificial intelligence systems	33 KB
	Structural approach The structural approach refers to attempts to build artificial intelligence by modeling the structure of the human brain. The main modeled structural unit in perceptrons, as in most other brain modeling options, is the neuron. Later, other models emerged, which are usually called neural networks. These models differ in the structure of individual neurons, the topology of connections between them, and learning algorithms.

The purpose of this book is to teach the reader the basics of microprocessor technology. A certain initial level of knowledge in radio engineering is assumed. I define this level as a specialist or amateur familiar with radio and pulse technology. It is not the purpose of this book to explain what resistors, capacitors, or transistors are. It is assumed that the reader is familiar with this and with the circuitry of analog devices, but is eager to learn what microprocessor devices are and learn how to design them himself. At the beginning of the book, the general principles of the digital representation of a signal are revealed, concepts such as logical elements, a digital signal, and the principles of storing and processing digital information are revealed. It also describes the principle of operation of those elements of digital technology that we will need in the future when we learn to build a microprocessor system. A description of all these elements is given in the book only to the extent necessary for a quick understanding of the basic principles of constructing microprocessor systems. For a more complete understanding of the operation of each element, I recommend that you refer to my website called “Digital chips and microprocessors” http:// www.mirmk.ru.

As an example of a microprocessor device, this book takes a real design developed by the author - a satellite dish positioner. The positioner is designed to automate the control of rotation of a household satellite dish. It is able to remember up to 99 positions (directions to the satellite), and then automatically install the antenna in any of these positions. To do this, you just need to select the number of this position using the remote control, or using the buttons on the front panel of the device. The positioner circuit and program were developed by the author of the book. The prototype was manufactured and tested using a standard foreign-made proprietary rotary device (motor, gearbox, reed switch sensor). The controller is based on the AT 89C 2051 microcontroller from Atmel ( www.atmel.com or www.atmel.ru). In this regard, the study of microprocessors will also be carried out using the AT 89C 2051 processor as an example. Currently, Atmel has switched to more modern processors such as AVR. However, from my point of view, building microprocessor devices on this processor is completely justified, since its parameters are perfect for this task, and the price of the AT 89C 2051 processor is significantly lower compared to any processor from the AVR family.

The book examines in detail the schematic diagram of the positioner and each of its components. Then the structure of the control program is given. The full text of the program is given in the appendix (floppy disk). The final chapters describe basic programming techniques, using specific software modules as examples.

The author hopes that this book will be useful to a wide range of specialists and radio amateurs and will be grateful for any comments and comments on the book. Please send all comments to the address Crimea, Simferopol, st. Russian, 194 or by E-mail: [email protected]. It should be noted that the text published here is the very first draft of the book. Since his writing, the book has been written in full and published in 2004. Then the book underwent quite significant changes and has already gone through about ten reprints. You can order the latest edition of the book in paper version at a discounted price by going to the appropriate page on this website

Educational program for beginners

Chapter 1. What is a microprocessor.

What is a microprocessor? And how is it different from a microcontroller?

In general, the processor is one of the components of a computer. Before the microprocessor (that is, the processor on a single chip) was invented, entire processor units existed. On large computers. To clarify the issue, you need to understand what a computer is. A computer is a device for automatic information processing. Moreover, information on the computer is presented in the form of numbers. Any computer system consists of the following main parts: Processor, Memory unit, I/O ports. Our task is not to study ancient types of computers. In the future we will talk about microprocessors and microcontrollers. So:

ü Memory. This is a set of cells, each of which stores one number. Moreover, this is not exactly the number that we are used to dealing with. This is a simplified computer number. Typically, each memory cell can store a number ranging from zero to 255. This will be discussed in more detail below.

ü I/O ports. These are some kind of microcircuits with the help of which a microprocessor system can communicate with the outside world. Through the input ports, the computer system receives information from the outside, and through the output ports it produces the results of its work and controls external devices. Only thanks to these same I/O ports, devices such as a keyboard, mouse, disk drives, CD-ROM, etc. are connected to the computer. Those readers who are familiar with computers may have heard the terms “parallel port” (LPT) and “serial port” (COM). So in this case we are talking about a completely different concept. These are just similar terms. Parallel and, especially, serial ports of a computer are entire, rather complex circuits, which in turn are controlled using input/output ports. You also don’t need to think that the keyboard and mouse use only input ports, and the display uses an output port. To control most computer devices, both input and output ports of the microprocessor system are used. You may be surprised that I refer to both a hard drive and a floppy drive as external devices. There, inside the computer, there are many more devices hidden that are external to the microprocessor, although they are often located not only inside the computer, but also directly on the motherboard - the main board of the computer.

ü CPU. The processor is the most important part, the heart of the entire system. It is designed to perform various sequences of actions with numbers in memory and with data in I/O ports. And that's all!

All three parts of the computer system are interconnected by so-called data buses. These buses carry digital signals from the processor to the memory module and I/O ports and back to the processor.

Rice. 1.

What can the processor do with these numbers? Yes, what can you do with them? It can read them from different memory cells, add, subtract, compare, then write to the same or other memory cells. It can also perform logical (Boolean) operations with numbers (I will describe what this is in detail below). More powerful processors can even multiply and divide numbers. Well, some special operations that we will definitely analyze when we study the operation of the microprocessor in more detail.

The processor does much less with I/O ports than with memory cells. After all, input ports are devices to which some electrical signals are received from the outside and the processor reads them in the form of the same numbers. And output ports are certain devices to which the processor can supply various numbers. And these numbers turn into electrical signals that control any external devices.

That's basically all the processor can do. But this is enough to perform all the miracles that we are used to seeing from computers. It turns out that everything in the world can be described in numbers. And text, and images, and sounds, including music. Scientists and mathematicians did a good job. They were able to develop mathematical models of all these processes. Just count faster! But modern processors can do this! Of course, modern processors have a much larger instruction set. But, basically, these are specialized group commands that replace any frequently used set of simpler ones. Our book does not set out to study modern microprocessors for personal computers. Our task is small specialized microprocessor devices. Such as, for example, some tricky timer, a washing machine control system or a satellite dish control unit. They have a common name: microprocessor controllers. This is where we will direct our attention.

Well, what is this wonderful device – a microprocessor? He reads and calculates and writes and does so many different smart things! How can he do all this? Apparently a very smart chip? In fact, a microprocessor is simply an automatic machine that performs the operations contained in it according to the PROGRAM. A program is a sequence of commands for the processor, written in the same memory, also in the form of numbers. Sometimes, however, memory is divided into two parts: program memory and data memory. The processor contains a simple algorithm. Immediately after turning on or after the arrival of a reset signal ( Reset), the processor begins to read from the memory area that is allocated for storing programs, number by number, one by one. Each such number encodes a command. A command is one of the actions that the microprocessor can perform. The number with which the command is encoded is called the operation code. The processor reads the opcode and performs the operation. Then it reads the following code and executes it again. So it reads these codes sequentially and executes them. This is the process of executing the program. Who wrote these codes into memory? Programmer! The programmer first came up with a program. Then I wrote it into a memory chip. I inserted the chip into the microprocessor system and turned on the power. The system started working. Here's a smart car for you. Vulgar machine gun.

Microprocessor controllers use so-called read-only memory devices (ROM) to store programs. In English it sounds like ROM (read only memory). They are called permanent because once information is written there, it does not change there. Recording is a special process performed using special devices - ROM programmers. Information is stored in them by burning certain areas of the chip. I downloaded it once and have been using this information for a long time. This is very suitable for storing a microprocessor controller program. The microprocessor can only read from such memory. He won't be able to write anything there. If he tries to write information there, nothing bad will happen. What will remain in memory is what was there before the recording attempt. In addition to the permanent storage device, the system must necessarily have memory made on RAM chips. That is, random access memory (RAM). In English RAM. The processor can write information to this memory and then read it. No program can do without a certain number of memory cells for storing many intermediate results and auxiliary values. RAM serves for these purposes.

Well, what are microcontrollers? Sometimes we read "AT 89C 2051 Microcontroller". A microcontroller is a child of further integration; it is an entire microprocessor system on one chip! One chip contains all the components of a microprocessor system: memory, input/output ports and the processor itself. In addition, some external (relative to the processor) devices are often located there (such devices are often called “peripheral”): timers, interrupt devices, comparators, etc. You will learn the meaning of these still unclear terms in subsequent chapters. In general, there is some confusion with the concepts of “microprocessor” and “microcontroller”. What I just called a microcontroller is sometimes also called a microprocessor. To understand what we are talking about, follow the context of the information provided.

According to the above definition, a microprocessor system is a collection of interacting LSIs of a microprocessor set (sometimes supplemented by LSIs from other sets) assembled into a single whole, organized into a system, i.e., a computing or control system with a microprocessor as an information processing unit. General block diagram. The typical structure of a microprocessor system is shown in Fig. 3. Let us briefly describe the node-modules included in its composition, with the exception of the already described microprocessor.

A clock pulse generator is a source of a sequence of rectangular pulses, with the help of which events are controlled in time. It specifies the instruction cycle—the time interval required to read a sample instruction from memory and execute it. The command cycle consists of a certain sequence of elementary actions called states (cycles). Some microprocessors do not require an external clock generator; it is contained directly in the circuitry of the single-chip microprocessor.

The system's main memory (external to the microprocessor) consists of ROM and RAM.

Read-only memory (ROM) is a device that stores a program (and, if necessary, a set of constants). The contents of the ROM cannot be erased. It is used as the memory of a program compiled in advance by the manufacturer in accordance with the requirements of its users. In such cases, the program is said to be hard-wired into the storage device. To implement another program, it is necessary to use another ROM or part of it. You can only select words stored there from the ROM, but you cannot add new ones, erase or replace the recorded words with others. It is like a printed table of bond winnings: you can only read the numbers there, but you cannot replace them or add new ones.

In addition to ROM, PROM and RPROM are also used.

Programmable read-only memory (PROM) differs from ROM in that the user can independently program the ROM (enter a program into it) using a special device - a programmer, but only once (after entering the program, the contents of the memory can no longer be changed).

A reprogrammable read-only memory (RPM), also called an erasable ROM, has the following feature: stored information can be erased several times (in the process, it is destroyed). In other words, the EPROM allows reprogramming, carried out using a programmer. This makes it easier to correct detected errors and allows you to change the contents of memory.

Random access memory (RAM), otherwise called random access memory (RAM) or random access memory (RAM), serves as a memory for data to be processed and the results of calculations, and in some microprocessor systems, also for programs that change frequently. Its characteristic property is that the time required to access any memory cell does not depend on the address of this cell. RAM allows both writing and reading words. In relation to this storage device, an analogy with a blackboard on which numbers are written in chalk is acceptable: they can be read out many times without destroying them, and if necessary, the number can be erased and a new one can be written in the free space. It should be borne in mind that the information contained in the RAM disappears or is erased if the supply voltage is interrupted.

The interface is called the interface device. This is a simplified definition. In a more strict interpretation, an interface is understood as a set of electrical, mechanical and software tools that allow you to connect system modules with each other and with peripheral devices. Its components are hardware for data exchange between nodes and software - a protocol that describes the procedure for interaction of modules during data exchange. The microprocessor system interface refers to machine interfaces. In a microprocessor system, special interface LSIs are used to interface peripheral devices with the system (in Fig. 2 they are shown in the form of input interface and output interface modules). These LSIs are characterized by versatility, achieved by programmatically changing the functions they perform.

Simpler tasks are solved by I/O ports - circuits designed (programmed) to exchange data with specific peripheral devices: receiving data from a keyboard or reader, transmitting it to a display, teletypewriter, etc.

The port is a medium-integrated circuit containing an addressable multi-mode I/O buffer register (MBR) with tristable output circuits (discussed below when describing the RAM circuit), control logic, and a connector for connecting I/O devices. Port reprogramming options are limited.

When the peripheral devices that are part of a microprocessor system are complex and perform numerous different operations, a sophisticated interface called a peripheral programmable adapter is used for interfacing. It contains a set of built-in ports and other registers that facilitate programming and timing coordination. Several simple I/O devices can be connected to one peripheral programmable adapter. Such an interface is considered a universal interface with wide application, since it can be combined with almost all available peripheral devices.

Many microprocessor systems and microcomputers are characterized by a discrepancy between the relatively high speed of information processing inside the microprocessor and the low speed of data exchange between modules via the interface.

The input device enters data to be processed and commands into the system. The output device converts the output data (the result of information processing) into a form convenient for user perception or storage. Input/output devices include units for reading information from punched tape and magnetic tape (or writing to them), cassette recorders, floppy disks, keyboards, displays, analog-to-digital and digital-to-analog converters, plotters, teletypes, etc.

Next, the subject of our attention will be the system buses. A bus is a group of transmission lines used to perform a specific function (one line for each bit transmitted). The peculiarity of the structure of a microprocessor system lies in the backbone organization of connections between its constituent modules. It is carried out using three buses. They transmit all the information and signals necessary for the operation of the system. These buses connect the microprocessor with external memory (RAM, ROM) and input-output interfaces, resulting in the possibility of exchanging data between the microprocessor and other system modules, as well as transmitting control signals.

Let's consider the purpose and functions of each of the three buses (using the example of an 8-bit microprocessor) shown in Fig. 3.

Data bus. This is a bidirectional bus: through it, data can be sent either to or from the microprocessor (in Fig. 3, this feature of the data bus is emphasized by an arrow with two points, one of which faces the microprocessor, and the other away from it). It is necessary to emphasize once again that simultaneous data transfer in both directions is impossible. These procedures are spaced apart in time as a result of time multiplexing.

Address bus (or address bus). It transmits information in only one direction - from the microprocessor to memory or input-output modules.

Control bus. Serves to transmit signals that determine interaction and synchronization of the operation of all system modules and internal components of the microprocessor. One part of the control bus lines serves to transmit signals coming from the microprocessor (in Fig. 3 this is conventionally shown by an arrow, the tip of which is directed to the right), and the other part of the lines transmits signals to the microprocessor (in Fig. 3 - an arrow with the tip directed left).

The advantage of the bus structure is the ability to connect new modules to the microprocessor system, for example, several blocks of RAM and ROM to obtain the required memory capacity.